View SAF-XC836MT-2FRA_1374044.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

data sheet v1.2 2011-03 microcontrollers xc835/836 8-bit single-chip microcontroller
edition 2011-03 published by infineon technologies ag 81726 munich, germany ? 2011 infineon technologies ag all rights reserved. legal disclaimer the information given in this document shall in no event be regarded as a guarantee of conditions or characteristics. with respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, infin eon technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation, warr anties of non-infringement of intellectual property rights of any third party. information for further information on technology, delivery terms and conditions and prices, please contact the nearest infineon technologies office ( www.infineon.com ). warnings due to technical requirements, components may contain dangerous substances. for information on the types in question, please contact the nearest infineon technologies office. infineon technologies components may be used in life-support devices or systems only with the express written approval of infineon technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system or to affect the safety or effectiveness of that device or system. life support devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain and/or protect human life. if they fail, it is reasonable to assume that the health of the user or other persons may be endangered.
data sheet v1.2 2011-03 microcontrollers xc835/836 8-bit single-chip microcontroller
xc835/836 data sheet v1.2, 2011-03 xc835/836 data sheet revision history: v1.2 2011-03 previous versions: v 1.1 page subjects (major cha nges since la st revision) page 3 , page 46 , page 49 tssop-28-9 package fo r automotive ha s been updated to tssop-28-12. we listen to your comments is there any informati on in this document that you feel is wrong, uncle ar or missing? your feedback will help us to continuously improve the quality of this document. please send your proposal (including a reference to th is document) to: mcdocu.comments@infineon.com
xc835/836 table of contents data sheet 1 v1.2, 2011-03 1 summary of features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2 general device information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.1 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.2 logic symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.3 pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.4 pin definitions and func tions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.5 memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.6 jtag id . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.7 chip identification num ber . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3 electrical parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.1 general parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.1.1 parameter interpretation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.1.2 absolute maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.1.3 operating condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.2 dc parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.2.1 input/output characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.2.2 supply threshold characteristic s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 3.2.3 adc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 3.2.3.1 adc conversion timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 3.2.3.2 out of range comparator characteristic s . . . . . . . . . . . . . . . . . . . . . 32 3.2.4 flash memory parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 3.2.5 power supply current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 3.3 ac parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 3.3.1 testing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 3.3.2 output rise/fall times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 3.3.3 oscillator timing and wake-up timing . . . . . . . . . . . . . . . . . . . . . . . . . 40 3.3.4 on-chip oscillator characteri stics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 3.3.5 ssc timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 3.3.5.1 ssc master mode timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 3.3.5.2 ssc slave mode timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 3.3.6 spd timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 4 package and qua lity declaration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 4.1 package parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 4.2 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 4.3 quality declaration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 table of contents
xc835/836 summary of features data sheet 1 v1.2, 2011-03 1 summary of features the xc835/836 has the following features: ? high-performance xc800 core ? compatible with sta ndard 8051 processor ? two clocks per machine cycl e architecture (for memory access without wait state) ? two data pointers ? on-chip memory ? 8 kbytes of boot rom, li brary rom and user routines ? 256 bytes of ram ? 256 bytes of xram ? 4/8 kbytes of flash (includes memory protection strategy) ? i/o port supply at 2.5 v - 5.5 v and core logic supply at 2.5 v (generated by embedded voltage regulator) figure 1 xc835/836 functional units ? power-on reset generation ? brownout detection for io s upply and core logic supply ? 48 mhz on-chip osc for clock generation ? loss-of-clock detection (more features on next page) port 0 port 1 port 2 xc800 core uart adc 10-bit 8-channel boot rom 8k bytes xram 256 bytes ram 256 bytes on-chip debug support timer 0 16-bit timer 1 16-bit timer 2 16-bit watchdog timer ssc 8/4k bytes flash capture/compare unit 16-bit compare unit 16-bit 8-bit digital i/o 6-bit digital i/o 8-bit digital/ analog input iic mdu led and touch sense controller real-time clock port 3 cordic 3-bit digital i/o
xc835/836 summary of features data sheet 2 v1.2, 2011-03 features: (continued) ? power saving modes ? idle mode ? power-down mode with wake-up capability via real-time clock event ? clock gating control to each peripheral ? programmable 16-bit watchd og timer (wdt) running on independent oscillator with programmable window feature for refresh operation and warning prior to overflow ? three general pu rpose i/o ports ? 4 high current i/o ? 2 high sink i/o ? up to 25 pins as digital i/o ? up to 8 pins as digital/analog input ? up to 8 channels, 10-bit a/d converter ? support up to 7 di fferential input channel ? results filtering by data re duction or digital low-pass filt er, for up to 13-bit results ? up to 8 channels, ou t of range comparator ? three 16-bit timers ? timer 0 and time r 1 (t0 and t1) ? timer 2 (t2) ? real-time clock with 32.768 khz crystal pad ? 16-bit vector computer for field-oriented control (foc) ? multiplication/division unit (m du) for arithmetic calculation ? cordic unit for trigonometric calculation ? capture and compare unit fo r pwm signal generation (ccu6) ? a full-duplex or half-dupl ex serial interface (uart) ? synchronous serial channel (ssc) ? inter-ic (iic) serial interface ? led and touch-sense controller (ledtscu) ? software libraries to su pport fixed-point contro l and eeprom emulation ? on-chip debug support via single pin dap interface (spd) ? packages: ? pg-dso-24 ? pg-tssop-28 ? temperature range t a : ? saf (-40 to 85 c)
xc835/836 summary of features data sheet 3 v1.2, 2011-03 xc835/836 variant devices the xc835/836 product family features devices with di fferent configurations, program memory sizes, packages op tions and temperature profil es, to offer cost-effective solutions for different ap plication requirements. the list of xc835/836 device configurations are summarized in table 1 . the type of packages available are dso-24 for xc835 and tssop-28 for xc836. table 2 shows the device sales type av ailable, based on above device. as this document refe rs to all the derivati ves, some descripti on may not apply to a specific product. for simplicity, all versions are referred to by the term xc835/836 throughout this document. table 1 device configuration device name mdu and cordi c module ledtscu module xc835/836 no no xc835/836m yes no xc835/836t no yes xc835/836mt yes yes table 2 device profile sales type device type program memory (kbytes) temp- erature profile ( c) package type quality profile saf-xc835mt-2fgi flash 8 -40 to 85 pg-dso-24-1 industrial saf-xc836-2fri flash 8 -40 to 85 pg-tssop-28-1 industrial saf-xc836t-2fri flash 8 -40 to 85 pg-tssop-28-1 industrial saf-xc836m-2fri flash 8 -40 to 8 5 pg-tssop-28-1 industrial saf-xc836m-1fri flash 4 -40 to 8 5 pg-tssop-28-1 industrial saf-xc836mt-2fri flash 8 -40 to 85 pg-tssop-28-1 industrial SAF-XC836MT-2FRA flash 8 -40 to 85 pg-tssop-28-12 automotive saf-xc836mt-1fra flash 4 -40 to 85 pg-tssop-28-12 automotive sak-xc836mt-2fra flash 8 -40 to 125 pg-tssop-28-12 automotive sak-xc836mt-1fra flash 4 -40 to 1 25 pg-tssop-28-12 automotive
xc835/836 summary of features data sheet 4 v1.2, 2011-03 ordering information the ordering code for infi neon technologies microcontrollers provides an exact reference to the requ ired product. this or dering code identifies: ? the derivative itself, i.e. its function se t, the temperature range, and the supply voltage ? the package and the type of delivery for the available orderi ng codes for the xc835/836, plea se refer to your responsible sales representative or your local distributor.
xc835/836 general device information data sheet 5 v1.2, 2011-03 2 general device information chapter 2 contains the block diagram, pin configur ations, definitions an d functions of the xc835/836. 2.1 block diagram the block diagram of the xc835/836 is shown in figure 2 . figure 2 xc835/836 block diagram port 0 port 1 led and touch sense controller 8-kbyte boot rom 1) 256-byte ram + 64-byte monitor ram 256-byte xram 4/8-kbyte flash xc800 core t0 & t1 uart 1) includes 1-kbyte monitor rom p0.0 - p0.7 p1.0 - p1.5 clock generator 48 mhz on-chip osc internal bus v ddp v ssp v ssc xc83x wdt ssc iic rtc ccu 6 adc port 2 p2.0 ? p2.7 port 3 p3.0 - p3.2 xtal 75 khz on-chip osc timer 2 scu evr cordic mdu vector computer ocds
xc835/836 general device information data sheet 6 v1.2, 2011-03 2.2 logic symbol the logic symbol of th e xc835/836 is shown in figure 3 . figure 3 xc835/836 logic symbol xc836 v ddp v ssp v ddc port 0 8-bit port 1 6-bit port 2 8-bit xc835 v ddp v ssp v ddc port 0 8-bit port 1 6-bit port 2 4-bit port 3 3-bit port 3 3-bit
xc835/836 general device information data sheet 7 v1.2, 2011-03 2.3 pin configuration the pin configuration of the xc835 in figure 4 . figure 4 xc835 pin configurat ion, pg-dso-24 package (top view) 1 2 3 4 5 6 7 8 9 10 11 12 14 13 23 22 21 20 19 18 17 16 15 24 xc835 p1.0/spd_2/rxd_2/t2ex_2/exint0_2/col0_0/ cout60_0/txd_1 p1.4/exint5/col4/cout62_0/cout63_2 p0.6/spd_1/rxd_1/sda_0/mtsr_1/mrst_0/exint0_1/ t2ex_0/line6/tsin6/txd_0/col2_1/cola_2 p0.5/rxd_0/mtsr_0/mrst_1/exint0_0/line5/tsin5/ cout62_1/txd_4/col1_1/exf2_3 p1.3/cc61_0/ col3_0/cc61_0/ exf2_2 p0.1/t0_0/cc61_1/mtsr_3/mrst_2/t13hr_0/ ccpos1_0/line1/tsin1 p0.2/t1_0/cc62_1/scl_1/ccpos2_0/line2/tsin2 p3.0/xtal4/scl_2/sck_1/exint2_1/col6 p3.1/xtal3/rxd_4/rtcclk/mtsr_4/ mrst_4/exint0_5/cola_0/exf2_1 p3.2/spd_0/rxd_3/sda_2/mtsr_5/ mrst_5/exint 0_6/t2ex_7/ txd_3 p1.5/cc62_0/col5/cola_1 p0.0/t2_0/t13hr_1/mtsr_2/mrst_3/t12hr_0/ ccpos0_0/line0/tsin0/cout61_1 v ddp v ssp v ddc p2.1/ccpos1_1/rxd_5/mtsr_6/t0_1/exint1_1/an1 p1.2/exint 4/ col2_0/cout61_0/cout63_1 p2. 2/ ccpos2_1/ t12hr_3/t 13hr_3/sck_3/ t1_1/exint 2_0/an2 p0.7/scl_3/line7/tsin7/txd_5/cout63_0/ col3_1/cola_3 p1.1/cc60_0/col1_0/txd_2 p2.0/ccpos0_1/t12hr_2/t13hr_2/t2ex_3/ t2_1/exint 0_3/an0 p0.4/t2ex_1/scl_0/sck_0/exint1_0/ctrap_1/ line4/tsin 4/ exf2_0/col 0_1/col3_2/ cola_4 p0.3/cc60_1/sda_1/ctrap_0/line3/tsin3 p2.3/ccpos0_2/ctrap_2/t2_2/exint3/an3
xc835/836 general device information data sheet 8 v1.2, 2011-03 the pin configuration of the xc836 in figure 5 . figure 5 xc836 pin configurat ion, pg-tssop-28 package (top view) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 18 17 16 15 27 26 25 24 23 22 21 20 19 28 xc836 p2.6/sck_2/exint6/an6 p2.5/t12hr_7/t13hr_7/an5 p2.4/t12hr_5/t13hr_5/t2_3/an4 p1.4/exint5/col4/cout62_0/cout63_2 p0.6/spd_1/rxd_1/sda_0/mtsr_1/mrst_0/exint0_1/ t2ex_0/line6/tsin6/txd_0/col2_1/cola_2 p0.5/rxd_0/mtsr_0/mrst_1/exint0_0/line5/ tsin5/cout62_1/txd_4/col1_1/exf2_3 p0.1/t0_0/cc61_1/mtsr_3/mrst_2/t13hr_0/ ccpos1_0/line1/tsin1 p0.2/t1_0/cc62_1/scl_1/ccpos2_0/line2/tsin2 p3.0/xtal4/scl_2/sck_1/exint2_1/col6 p3.1/xtal3/rxd_4/rtcclk/mtsr_4/ mrst_4/exint 0_5/cola_0/ exf2_1 p3.2/spd_0/rxd_3/sda_2/mtsr_5/mrst_5/ exint0_6/t2ex_7/txd_3 p1.5/cc62_0/col5/cola_1 p0.0/t2_0/t13hr_1/mtsr_2/mrst_3/t12hr_0/ ccpos0_0/line0/tsin0/cout61_1 v ddp v ssp v ddc p2. 1/ ccpos1_1/ rxd_5/ mtsr_6/t 0_1/ exint1_1/an1 p2.2/ccpos2_1/t12hr_3/t13hr_3/sck_3/ t1_1/exint2_0/an2 p0.7/scl_3/line7/tsin7/txd_5/cout63_0/ col3_1/cola_3 p2.7/rxd_6/t2ex_6/mtsr_7/exint0_4/an7 p2.3/ccpos0_2/ctrap_2/t2_2/exint3/an3 p2.0/ccpos0_1/t12hr_2/t13hr_2/t2ex_3/ t2_1/exint0_3/an0 p0.4/t2ex_1/scl_0/sck_0/exint1_0/ctrap_1/ line4/tsin4/exf2_0/col0_1/col3_2/cola_4 p0.3/cc60_1/sda_1/ctrap_0/line3/tsin 3 p1.0/spd_2/rxd_2/t2ex_2/exint0_2/ col0_0/cout60_0/txd_1 p1.3/cc61_0/ col3_0/cc61_0/ exf2_2 p1.2/exint4/col2_0/cout61_0/cout63_1 p1.1/cc60_0/col1_0/txd_2
xc835/836 general device information data sheet 9 v1.2, 2011-03 2.4 pin definitions and functions the functions and defa ult states of the xc 835/836 external pi ns are provided in table 3 . table 3 pin definitions and functions for xc835/836 symbol pin number tssop28/ ds024 type reset state function p0 i/o port 0 port 0 is a bidirectional general purpose i/o port. it can be used as al ternate functions for ledtscu, timer 0, 1 and 2, ssc, ccu6, iic, spd and uart. p0.0 21/19 hi-z t2_0 timer 2 input t13hr_1 ccu6 timer 13 hardware run input mtsr_2 ssc master transmit output/ slave receive input mrst_3 ssc master receive input t12hr_0 ccu6 timer 12 hardware run input ccpos0_0 ccu6 hall input 0 tsin0 touch-sense input 0 line0 led line 0 cout61_1 output of capture/compare channel 1
xc835/836 general device information data sheet 10 v1.2, 2011-03 p0.1 22/20 hi-z t0_0 timer 0 input cc61_1 input/output of capture/compare channel 1 mtsr_3 ssc slave receive input mrst_2 ssc master receive input/ slave transmit output t13hr_0 ccu6 timer 13 hardware run input ccpos1_0 ccu6 hall input 1 tsin1 touch-sense input 1 line1 led line 1 p0.2 23/21 hi-z t1_0 timer 1 input cc62_1 input/output of capture/compare channel 2 scl_1 iic clock line ccpos2_0 ccu6 hall input 2 tsin2 touch-sense input 2 line2 led line 2 p0.3 24/22 hi-z cc60_1 input/o utput of capture/compare channel 0 sda_1 iic data line ctrap_0 ccu6 trap input tsin3 touch-sense input 3 line3 led line 3 table 3 pin definitions and functions for xc835/836 (cont?d) symbol pin number tssop28/ ds024 type reset state function
xc835/836 general device information data sheet 11 v1.2, 2011-03 p0.4 11/9 pd t2ex_1 timer 2 external trigger input sck_0 ssc clock input/output scl_0 iic clock line ctrap_1 ccu6 trap input exint1_0 external interrupt input 1 tsin4 touch-sense input 4 line4 led line 4 exf2_0 timer 2 overflow flag col0_1 led column 0 col3_2 led column 3 cola_4 led column a p0.5 10/8 hi-z rxd_0 uart receive input mtsr_0 ssc master transmit output/ slave receive input mrst_1 ssc master receive input exint0_0 external interrupt input 0 tsin5 touch-sense input 5 line5 led line 5 cout62_1 output of capture/compare channel 2 txd_4 uart transmit output col1_1 led column 1 exf2_3 timer 2 overflow flag table 3 pin definitions and functions for xc835/836 (cont?d) symbol pin number tssop28/ ds024 type reset state function
xc835/836 general device information data sheet 12 v1.2, 2011-03 p0.6 9/7 pu spd_1 spd input/output rxd_1 uart receive input sda_0 iic data line mtsr_1 ssc slave receive input mrst_0 ssc master receive input/ slave transmit output exint0_1 external interrupt input 0 t2ex_0 timer 2 external trigger input tsin6 touch-sense input 6 line6 led line 6 txd_0 uart transmit output col2_1 led column 2 cola_2 led column a p0.7 28/2 hi-z scl_3 iic clock line tsin7 touch-sense input 7 line7 led line 7 txd_5 uart transmit output/ 2-wire uart bsl transmit output cout63_0 output of capture/compare channel 3 col3_1 led column 3 cola_3 led column a p1 i/o port 1 port 1 is a bidirectional general purpose i/o port. it can be used as alte rnate functions for ccu6, ledtscu, spd, uart and timer 2 table 3 pin definitions and functions for xc835/836 (cont?d) symbol pin number tssop28/ ds024 type reset state function
xc835/836 general device information data sheet 13 v1.2, 2011-03 p1.0 16/14 hi-z spd_2 spd input/output rxd_2 uart receive input t2ex_2 timer 2 external trigger input exint0_2 external interrupt input 0 col0_0 led column 0 cout60_0 output of capture/compare channel 0 txd_1 uart transmit output p1.1 15/13 hi-z cc60_0 input/o utput of capture/compare channel 0 col1_0 led column 1 txd_2 uart transmit output p1.2 14/12 hi-z exint4 external interrupt input 4 col2_0 led column 2 cout61_0 output of capture/compare channel 1 cout63_1 output of capture/compare channel 3 p1.3 13/11 hi-z cc61_0 input/o utput of capture/compare channel 1 col3_0 led column 3 exf2_2 timer 2 overflow flag p1.4 19/17 hi-z exint5 external interrupt input 5 col4 led column 4 cout62_0 output of capture/compare channel 2 cout63_2 output of capture/compare channel 3 table 3 pin definitions and functions for xc835/836 (cont?d) symbol pin number tssop28/ ds024 type reset state function
xc835/836 general device information data sheet 14 v1.2, 2011-03 p1.5 20/18 hi-z cc62_0 input/o utput of capture/compare channel 2 col5 led column 5 cola_1 led column a p2 i port 2 port 2 is a general purpos e input-only po rt. it can be used as inputs for a/d converter and out of range comparator, ccu6, timer 2, ssc and uart. p2.0 8/6 hi-z ccpos0_1 ccu6 hall input 0 t12hr_2 ccu6 timer 12 hardware run input t13hr_2 ccu6 timer 13 hardware run input t2ex_3 timer 2 external trigger input t2_1 timer 2 input exint0_3 external interrupt input 0 an0 analog input 0 / out of range comparator channel 0 p2.1 7/5 hi-z ccpos1_1 ccu6 hall input 1 rxd_5 uart receive input mtsr_6 ssc slave receive input t0_1 timer 0 input exint1_1 external interrupt input 1 an1 analog input 1 / out of range comparator channel 1 table 3 pin definitions and functions for xc835/836 (cont?d) symbol pin number tssop28/ ds024 type reset state function
xc835/836 general device information data sheet 15 v1.2, 2011-03 p2.2 6/4 hi-z ccpos2_1 ccu6 hall input 2 t12hr_3 ccu6 timer 12 hardware run input t13hr_3 ccu6 timer 13 hardware run input sck_3 ssc clock input/output t1_1 timer 1 input exint2_0 external interrupt input 2 an2 analog input 2 / out of range comparator channel 2 p2.3 5/3 hi-z ccpos0_2 ccu6 hall input 0 ctrap_2 ccu6 trap input t2_2 timer 2 input exint3 external interrupt input 3 an3 analog input 3 / out of range comparator channel 3 p2.4 4/- hi-z t12hr_5 ccu6 ti mer 12 hardware run input t13hr_5 ccu6 timer 13 hardware run input t2_3 timer 2 input an4 analog input 4 / out of range comparator channel 4 p2.5 3/- hi-z t12hr_7 ccu6 ti mer 12 hardware run input t13hr_7 ccu6 timer 13 hardware run input an5 analog input 5 / out of range comparator channel 5 table 3 pin definitions and functions for xc835/836 (cont?d) symbol pin number tssop28/ ds024 type reset state function
xc835/836 general device information data sheet 16 v1.2, 2011-03 p2.6 2/- hi-z sck_2 ssc clock input/output exint6 external interrupt input 6 an6 analog input 6 / out of range comparator channel 6 p2.7 1/- hi-z rxd_6 uart receive input t2ex_6 timer 2 external trigger input mtsr_7 ssc slave receive input exint0_4 external interrupt input 0 an7 analog input 7 / out of range comparator channel 7 p3 i/o port 3 port 3 is a bidirectional general purpose i/o port. it can be used as alte rnate functions for iic, ledtscu, uart, timer 2, ssc, spd and 32.768 khz crystal pad. p3.0 26/24 pu scl_2 iic clock line sck_1 ssc clock input/output exint2_1 external interrupt input 2 col6 led column 6 xtal4 32.768 khz external oscillator output table 3 pin definitions and functions for xc835/836 (cont?d) symbol pin number tssop28/ ds024 type reset state function
xc835/836 general device information data sheet 17 v1.2, 2011-03 p3.1 25/23 pu rxd_4 uart receive input rtcclk rtc external clock input mtsr_4 ssc master transmit output/ slave receive input mrst_4 ssc master receive input exint0_5 external interrupt input 0 cola_0 led column a xtal3 32.768 khz external oscillator input exf2_1 timer 2 overflow flag p3.2 27/1 pu spd_0 spd input/output rxd_3 uart receive input/ uart bsl receive input sda_2 iic data line mtsr_5 ssc slave receive input mrst_5 ssc master receive input/ slave transmit output exint0_6 external interrupt input 0 t2ex_7 timer 2 external trigger input txd_3 uart transmit output/ 1-wire uart bsl transmit output v ddp 12/10 ? ? i/o port supply (2.5 v - 5.5 v) v ddc 18/16 ? ? core supply monitor (2.5 v) v ssp / v ssc 17/15 ? ? i/o port ground/ core supply ground table 3 pin definitions and functions for xc835/836 (cont?d) symbol pin number tssop28/ ds024 type reset state function
xc835/836 general device information data sheet 18 v1.2, 2011-03 2.5 memory organization the xc835/836 cpu operates in the following five address spaces: ? 8 kbytes of boot rom, li brary rom and user routines ? 256 bytes of internal ram ? 256 bytes of xram (xram can be read/written as program memory or external data memory) ? a 128-byte special function register area ? 4/8 kbytes of flash figure 6 illustrates the memory address spaces of the 4 kbyte flash devices. figure 7 illustrates the memory address spac es of the 8 kbyte flash devices. figure 6 memory map of xc835/836 with 4 kbytes of flash memory 0000 h 1000 h f000 h c000 h e000 h f100 h ffff h flash bank 0 4 kbytes boot rom 8 kbytes xram 256 bytes f000 h f100 h 0000 h ffff h special function registers indirect address direct address 80 h ff h 00 h code space external data space internal data space internal ram memory map user m ode xram 256 bytes 7f h internal ram b000 h flash bank 0 4 kbytes 1) a000 h in debug mode, this 64-byte address area is replaced by a 64-byte monitor ram. 40 h 1) physically one 4-kbyte flash bank , mapped to both address range .
xc835/836 general device information data sheet 19 v1.2, 2011-03 figure 7 memory map of xc835/836 with 8 kbytes of flash memory 0000 h 1000 h f000 h c000 h e000 h f100 h ffff h flash bank 0 4 kbytes boot rom 8 kbytes xram 256 bytes f000 h f100 h 0000 h ffff h special function registers indirect address direct address 80 h ff h 00 h code space external data space internal data space internal ram memory map user mode xram 256 bytes 7f h internal ram b000 h flash bank 1 4 kbytes 1) 2000 h a000 h in debug mode, this 64-byte address area is replaced by a 64-byte monitor ram. 40 h flash bank 1 4 kbytes 1) 1) physically one 4-kbyte flash bank , mapped to both address range . flash bank 1 is only available in 8-kbyte flash variant . 2) user bsl flash sector is only available in 8-kbyte flash variant . user bsl flash sector 64 bytes 2) ff40 h ff80 h
xc835/836 general device information data sheet 20 v1.2, 2011-03 2.6 jtag id jtag id register is a read-o nly register located inside th e jtag module, and is used to recognize the dev ice(s) connected to the jtag interface. its cont ent is shifted out when instruction register contains the idcode comma nd (opcode 04 h ), and the same is also true immediately after reset. the jtag id register contents for th e xc835/836 flash devices are given in table 4 . note: the asterisk (*) ab ove denotes all possible device configurations. table 4 jtag id summary device type device name jtag id flash xc835*-2fg 101b a083 h xc836*-2fr xc836*-1fr 101b b083 h
xc835/836 general device information data sheet 21 v1.2, 2011-03 2.7 chip identification number the xc835/836 identity (id) register is located at page 1 of address b3 h . the value of id register is 59 h . however, for easy identificati on of product variants, the chip identification number, which is an unique number assigned to each product variant, is available. the differentiatio n is based on the product a nd variant type information. two methods are prov ided to read a device?s ch ip identification number: ? in-application subr outine, get_chip_info ? boot-loader (bsl) mode a table 5 lists the chip identi fication numbers of xc 835/836 device variants. table 5 chip identification number product variant chip identification number xc835mt-2fg 59080001 h xc836-2fr 59080060 h xc836t-2fr 59080040 h xc836m-2fr 59080020 h xc836m-1fr 59080120 h xc836mt-2fr 59080000 h xc836mt-1fr 59080100 h
xc835/836 electrical parameters data sheet 22 v1.2, 2011-03 3 electrical parameters chapter 3 provides the characteristics of th e electrical parameters which are implementation-speci fic for the xc835/836. 3.1 general parameters the general parameters are described here to aid the us ers in interpreting the parameters mainly in section 3.2 and section 3.3 . 3.1.1 parameter interpretation the parameters listed in this section represent part ly the characteristics of the xc835/836 and partly it s requirements on the system. to aid interpreting the parameters easily when evaluating them for a design, they ar e indicated by the abb reviations in the ?symbol? column: ? cc ? these parameters indicate c ontroller c haracteristics, which are distinctive features of the xc835/836 and must be regarded for a system design. ? sr ? these paramete rs indicate s ystem r equirements, which must be provided by the microcontroller system in whic h the xc835/836 is designed in.
xc835/836 electrical parameters data sheet 23 v1.2, 2011-03 3.1.2 absolute maximum rating maximum ratings are the extreme limits to which the xc835/8 36 can be subjected to without permanent damage. note: stresses above those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditio ns above thos e indicated in the operational sections of this specification is not im plied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. during absolute maximum ra ting overload conditions ( v in > v ddp or v in < v ss ) the voltage on v ddp pin with respect to ground ( v ss ) must not exceed the values defined by the absol ute maximum ratings. table 6 absolute maximu m rating parameters parameter symbol limit values unit notes min. max. ambient temperature t a -40 125 c under bias storage temperature t st -65 150 c? junction temperature t j -40 150 c under bias voltage on power supply pin with respect to v ss v ddp -0.5 6 v maximum current per pin for p1[3:0] i m -115 115 ma input current on any pin during overload condition i in -10 10 ma absolute sum of all input currents during overload condition | i in |? 50 ma
xc835/836 electrical parameters data sheet 24 v1.2, 2011-03 3.1.3 operating condition the following operating conditions must not be exceed ed in order to ensure correct operation of the xc835/836. all parameters menti oned in the following tables refer to these operating co nditions, unless otherwise noted. table 7 operating condition parameters parameter symbol limit values unit notes/ conditions min. max. digital power supply voltage v ddp 3.0 5.5 v 2.5 3.0 v 1) 1) in this voltage range, limited operations are available in active mode. operations in power save modes are fully supported. digital core supply voltage 2) 2) v ddc is supplied by the on-chip evr. the limits are verified by design and production testing. v ddc 2.3 2.7 v cpu clock frequency f cclk 22.5 25.6 mhz typ. 24 mhz 7.5 8.5 mhz typ. 8 mhz ambient temperature t a -40 85 c saf-xc835/836...
xc835/836 electrical parameters data sheet 25 v1.2, 2011-03 3.2 dc parameters the electrical characteristic s of the dc parameters are detailed in this section. 3.2.1 input/output characteristics table 8 provides the characteri stics of the input/output pins of the xc835/836. table 8 input/output characterist ics (operating conditions apply) parameter symbol limit valu es unit test conditions min. max. output low voltage on port pins (all except p1) v olp cc ? 1.0 v i ol = 25 ma (5 v) i ol = 13 ma (3.3 v) ?0.4v i ol = 10 ma (5 v) i ol =5ma (3.3v) output low voltage on p1[3:0] v olp1 cc ? 1.0 v i ol = 50 ma (5 v) i ol = 25 ma (3.3 v) ?0.32v i ol = 20 ma (5 v) ?0.4v i ol = 10 ma (3.3 v ) output low voltage on p1[5:4] v olp2 cc ? 1.0 v i ol = 50 ma (5 v) i ol = 25 ma (3.3 v) ?0.4v i ol = 20 ma (5 v) i ol = 10 ma (3.3 v) output high voltage on port pins (all except p1) v ohp cc v ddp - 1.0 ?v i oh =-15ma (5v) i oh = -8 ma (3.3 v ) v ddp - 0.4 ?v i oh = -5 ma (5 v) i oh = -2.5 ma (3.3 v) output high voltage on p1[3:0] v ohp1 cc v ddp - 0.32 ?v i oh =-20ma (5v) v ddp - 1.0 ?v i oh =-25ma (3.3v) v ddp - 0.4 ?v i oh =-10ma (3.3v) output high voltage on p1[5:4] v ohp2 cc v ddp - 1.0 ?v i oh =-30ma (5v) i oh =-16ma (3.3v) v ddp - 0.4 ?v i oh =-10ma (5v) i oh =- 5 ma (3.3 v)
xc835/836 electrical parameters data sheet 26 v1.2, 2011-03 input low voltage on port pins v ilp sr ? 0.3 v ddp v cmos mode (5 & 3.3 v) input high voltage on port pins v ihp sr 0.7 v ddp ?vcmos mode (5 v & 3.3 v) input hysteresis 1) hys cc 0.08 v ddp ?vcmos mode (5v) 0.03 v ddp ? v cmos mode (3.3 v) 0.01 v ddp ? v cmos mode (2.5 v) pull-up current i pup sr ? -20 a v ih,min (5 v) -150 ? a v il,max (5 v) ?-5 a v ih,min (3.3 v) -100 ? a v il,max (3.3 v) pull-down current i pdp sr ? 20 a v il,max (5 v) 150 ? a v ih,min (5 v) ?5 a v il,max (3.3 v) 100 ? a v ih,min (3.3 v) input leakage current on port pins 2) (all except p1) i ozp cc -1 1 a0 < v in < v ddp , t a 125 c input leakage current on p1[3:0] 2) i ozp1 cc -3 3 a0 < v in < v ddp , t a 125 c input leakage current on p1[5:4] 2) i ozp2 cc -2 2 a0 < v in < v ddp , t a 125 c overcurrent threshold per pin for p1[3:0] 3) |i ocp1 | sr 60 115 ma v ddp =5v overload current on any pin i ovp sr -5 5 ma 4) absolute sum of overload currents | i ov |sr? 25 ma 4) table 8 input/output characterist ics (operating conditions apply) (cont?d) parameter symbol limit valu es unit test conditions min. max.
xc835/836 electrical parameters data sheet 27 v1.2, 2011-03 voltage on any pin during v ddp power off v po sr ? 0.3 v 5) maximum current per pin (excluding p1, v ddp and v ss ) i mp sr -15 25 ma ? maximum current per pin for p1[3:0] i mp1a sr -50 50 ma ? maximum current per pin for p1[5:4] i mp1b sr -30 50 ma ? maximum current into v ddp i mvddp sr ? 130 ma 4) maximum current out of v ss i mvss sr ? 130 ma 4) 1) not subjected to production test, verified by design/characterization. hysteresis is implemented to avoid meta stable states and switching due to internal ground bounc e. it cannot be guaranteed that it suppresses switching due to external system noise. 2) an additional error current ( i inj ) will flow if an overload current flows through an adjacent pin. 3) over current detection is available for 5v application only. 4) not subjected to production test, verified by design/characterization. 5) not subjected to production test, verified by design/char acterization. however, for applications with strict low power-down current requirements, it is mandatory that no active voltage source is supplied at any gpio pin when v ddp is powered off. table 8 input/output characterist ics (operating conditions apply) (cont?d) parameter symbol limit valu es unit test conditions min. max.
xc835/836 electrical parameters data sheet 28 v1.2, 2011-03 3.2.2 supply threshold characteristics table 9 provides the characteri stics of the supply thre shold in the xc835/836. figure 8 supply threshold parameters table 9 supply threshold paramete rs (operating conditions apply) parameters symbol limit values unit min. typ. max. v ddp prewarning voltage 1)2) 1) detection is enabled via sdcon register in active mode. it is automatically disabled in power down mode. detection should be disabled for v ddp less than maximum of v ddppw . 2) this parameter has a hysteresis of 50 mv. v ddppw cc 3.0 3.6 4.5 v v ddp brownout voltage in active mode 2)3) 3) detection is enabled via sdcon register. detection must be disabled for application with v ddp less than the specified values. v ddpboa cc 2.65 2.75 2.87 v v ddp brownout voltage in all power down mode 2)3) v ddpbopd 3.0 3.6 4.5 v v ddp system reset release voltage 2)4) 4) v ddpsrr and v ddcsrr must be met before the system reset is released. v ddpsrr cc 2.7 2.8 2.92 v v ddc prewarning voltage 2)5) 5) detection is enabled via sdcon register in active mode. it is automatically disabled in power down mode. v ddcpw cc 2.3 2.4 2.48 v v ddc brownout voltage in active mode 2) v ddcboa cc 2.25 2.3 2.42 v v ddc brownout voltage in power down mode 2) v ddcbopd cc 1.35 1.5 1.95 v v ddc system reset release voltage 2)4) v ddcsrr cc 2.28 2.3 2.47 v ram data retention voltage v ddcrdr cc 1.1 ? ? v vddp vddc v ddppw /v ddpbopd v ddcsrr v ddcpw v ddcboa v ddcrdr 5.0v 2.5v v ddcbopd v ddpboa v ddpsrr
xc835/836 electrical parameters data sheet 29 v1.2, 2011-03 3.2.3 adc characteristics the values in table 10 are given for an analog power supply of 5.0 v . the adc can be used with an analog po wer supply down to 3 v . but in this case, analog parameters may show a reduced performance. in the reduced vo ltage mode (2.5 v < v ddp < 3 v), the adc is not recommend ed to be used. table 10 adc characteristics (o perating conditions apply; v ddp = 5 v; f adci <= 12 mhz) parameter symbol lim it values unit test conditions / remarks min. typ. max. analog reference voltage v aref ? v ddp ? v connect internally to v ddp analog reference ground v agnd ? v ssp ? v connect internally to v ssp alternate analog reference ground v agndalt sr v ssp - 0.1 ?2.5 1) v connect to an0 in differential mode, see figure 9 . internal voltage reference v intref sr 1.19 1.23 1.28 v 4) analog input voltage range v ain sr v agnd ? v aref v? adc clock f adci 8 ? 16 mhz internal analog clock sample time t s cc (2 + inpcr0.stc) t adci s? conversion time t c cc see section 3.2.3.1 s? set-up time between conversions using internal voltage reference t setup sr ? 35 ? s 2)
xc835/836 electrical parameters data sheet 30 v1.2, 2011-03 total unadjusted error tue 3) cc ? ? 1 lsb8 8-bit conversion with internal reference 4) ? ? +4/-2 lsb10 10-bit conversion with internal reference 4)5) ? ? +14/-2 lsb12 12-bit conversion using the low pass filter 4) differential nonlinearity ea dnl cc ? ? +1.5/ -1 lsb 10-bit conversion 4) integral nonlinearity ea inl cc ? ? 1.5 lsb 10-bit conversion 4) offset ea off cc ? +4 ? lsb 10-bit conversion 4) gain ea gain cc ? -4 ? lsb 10-bit conversion 4) switched capacitance at an analog input c ainsw cc ? 2 3 pf 4)6) total capacitance at an analog input c aint cc ? ? 12 pf 4)6) input resistance of an analog input r ain cc ? 1.5 2 k ? 4) 1) 1.2 v at v ddp =3.0v. 2) not subject to production test, verified at cpu clock ( f sclk, cclk )=8mhz, t a =+25 c and v ddp =5v. 3) tue is tested at v aref = v ddp = 5.0 v and cpu clock ( f sclk, cclk )=8mhz. 4) not subject to production test, verified by design/characterization. 5) if a reduced positive reference voltage is used, tue will increase. if the positive reference is reduced by a factor of k, the tue will increased by 1/k. example:k = 0.8, 1/k = 1.25; 1.25 x tue = 2.5 lsb10. 6) the sampling capacity of the conversion c-network is pre-charged to v aref /2 before connecting the input to the c-network. because of the parasitic element s, the voltage measured at anx is lower than v aref /2. table 10 adc characteristics (o perating conditions apply; v ddp = 5 v; f adci <= 12 mhz) (cont?d) parameter symbol lim it values unit test conditions / remarks min. typ. max.
xc835/836 electrical parameters data sheet 31 v1.2, 2011-03 figure 9 differential like me asurement with internal 1.2v voltage reference, and ch0 gnd. figure 10 adc input circuits ad converter conversion control request control interrupt generation adc kernel result handling v 1.2vref v 1.2vgnd va_altgnd va_altref ain ch0 ain ch1 ain ch7 ... v ssp r ext analog input circuitry v ain c ext anx c ainsw r ain, on c aint -c ainsw
xc835/836 electrical parameters data sheet 32 v1.2, 2011-03 3.2.3.1 adc conversion timing conversion time, t c = t adc (1 + r (3+n+stc)), where ? r=ctc+3, ? ctc = conversion time control (globctr.ctc), ? stc = sample time control (inpcr0.stc), ? n = 8 or 10 (for 8-bit and 10-bit conversion respectively), ? t adc =1/ f adc 3.2.3.2 out of range comparator characteristics table 11 below shows the out of rang e comparator characteristics. table 11 out of range comparator ch aracteristics (operating conditions apply) parameter symbol limit values unit remarks min. typ. max. dc switching level v sensedc sr 60 125 270 mv above v ddp dc hysteresis v sensehys cc 30 ? ? mv 1) 1) not subject to production test, verified by design/characterization. pulse width t sensepw sr 300 ? ? ns anx > v ddp 1) switching delay t sensesd cc ? ? 400 ns anx >= v ddp +350mv 1) pulse switching level t sensepsl sr ? 250 ? mv @ 300 nsec 1) sr ? 60 ? mv @ 800 usec 1)
xc835/836 electrical parameters data sheet 33 v1.2, 2011-03 3.2.4 flash memory parameters the xc835/836 is delivered with all flash sectors erased (read all zeros). the data retention time of the xc835/836?s flash memory (i.e. the time after which stored data can still be retrie ved) depends on the number of times the flash memory has been erased and programmed. note: flash memory parameters are not subject to production test bu t verified by design and/or characterization. table 12 flash timing parameters (operating conditions apply) parameter symbol limit values unit remarks min. typ. max. read access time (per byte) t acc cc ? 125 ? ns programming time (per wordline) t pr cc ? 2.2 ? ms erase time (one or more sectors) t er cc ? 120 ? ms flash wait states n wsflash cc 0 cpu clock = 8 mhz 1cpu clock=24mhz table 13 flash data retent ion and endurance (opera ting conditions apply) retention endurance 1) 1) one cycle refers to the pr ogramming of all wordlines in a sector and erasing of sector. the flash endurance data specified in table 13 is valid only if the following conditions are fulfilled: - the maximum number of erase cycles per flas h sector must not e xceed 100,000 cycles. - the maximum number of erase cycles per flash bank must not exceed 300,000 cycles. - the maximum number of program cycles per flash bank must not exceed 2,500,000 cycles. size remarks 20 years 1,000 cycl es up to 8 kbytes 5 years 10,000 cycles 1 kbyte 2 years 70,000 cycles 512 bytes 2 years 100,000 cycles 128 bytes
xc835/836 electrical parameters data sheet 34 v1.2, 2011-03 table 14 emulated flash data retent ion and endurance based on eeprom emulation rom library (ope rating conditions apply) retention endurance 1) 1) these values show the maximum endurance. maximum endurance is the maximum possible unique data write if each data update is only 31 bytes. minimum endur ance cycle is the maximum possible unique data write if each data update is the same as the emulation size. the minimum endurance cycle can be calculated using the formulae [(max. endurance)*(31)/(emulation size)]. emulation size remarks 2 years 1,600,000 cycles 31 bytes 2 years 1,400,000 cycles 62 bytes 2 years 1,200,000 cycles 93 bytes 2 years 1,000,000 cycles 124 bytes
xc835/836 electrical parameters data sheet 35 v1.2, 2011-03 3.2.5 power supply current table 15 provides the characteri stics of the power supply current in th e xc835/836. table 15 power cons umption parameters 1) 2) (operating conditions apply) 1) the typical i ddp values are measured at t a =+25 c and v ddp = 5 v and 3.3 v. 2) the maximum i ddc values are measured under worst case conditions ( t a = + 125 c and v ddc =5v). parameter symbol limit va lues unit test condition typ. max. active mode i ddpa 23 28 ma 5 v / 3.3 v 3) 3) i ddp (active mode) is measured with: cpu clock and input clock to all peripherals running at 24 mhz (clkmode=0). 16 20 ma 5 v / 3.3 v 4) 4) i ddp (active mode) is measured with: cpu clock and input clock to all peripherals running at 8 mhz (clkmode=1). ?5 ma2.5v 5) 5) this value is based on the maximum load capacity of evr during v ddp = 2.5 v. not subject to production test, verified by design/characterisation. idle mode i ddpi 18 25 ma 5 v / 3.3 v 6) 6) i ddpi (idle mode) is measured with: cpu clock disabled, watchdog timer disabled, input clock to all peripherals enabled and running at 24 mhz (clkmode=0). ?5 ma2.5v 5) power down mode 1 i pdp1 35 a t a = 25 c 7) 7) i pdp1 , i pdp2 , i pdp3 and i pdp4 is measured at 5 v and 3.3 v with: wake-up port is programmed to be input with either internal pull devices enabled or driven externally to ensure no floating inputs. ?28 a t a = 85 c 7)8)9) 8) not subject to production test, verified by design/characterisation. 9) i pdp1 , i pdp2 , i pdp3 and i pdp4 has a maximum values of 120 ua at t a =+125 c. power down mode 2 i pdp2 68 a t a = 25 c 7)8) ?31 a t a = 85 c 7)8)9) power down mode 3 i pdp3 57 a t a = 25 c 7)8) ?30 a t a = 85 c 7)8)9) power down mode 4 i pdp4 57 a t a = 25 c 7) ?30 a t a = 85 c 7)8)9)
xc835/836 electrical parameters data sheet 36 v1.2, 2011-03 table 16 shows the maximum active current with in the device in the reduced voltage condition of 2.5 v < v ddp < 3.0 v. the active current cons umption needs to be below the specified values as according to the v ddp voltage. if the conditions are not met, a brownout reset may be triggered. table 17 provides the active current consumpt ion of some module s operating at 8 mhz active mode, 3 v power supply at 25 c. the typical values shown are used as a reference guide for device operatin g in reduced volt age conditions. table 16 active current consumpti on in reduced volt age condition v ddp 2.5v 2.6v 2.7v 2.8v maximum active current 7ma 13ma 20ma 25ma table 17 typical active current consumption 1) 2) 1) modules that are controllable by programming the register pmcon1. 2) not subject to production test, verified by design/characterisation. active current consumption symbol limit values unit test condition typ. baseload current 3) 3) baseload current is measured when the device is running in user mode with an endless loop in the flash memory. all modules in register pmcon1 are disabled. i cpuddc 6900 a modules including core, memories, uart, t0, t1 and evr. disable adc analog (globctr.anon = 0). adc 4) 4) adc active current is measured with: module enable, adc analog clock at 8mhz, running in parallel conversion request in autoscan mode for 4 channels i adcddc 3760 a set pmcon1.adc_dis to 0 and globectr. anon to 1 ssc 5) 5) ssc active curremt is measured with: module enabled, running in loop back mode at a baud rate of 1 mbaud i sscddc 460 a set pmcon1.ssc_dis to 0 ccu6 6) 6) ccu6 active current is measured with: module enabled, all timers running in 8 mhz, 6 pwm outputs are generated. i ccu6ddc 3320 a set pmcon1.ccu_dis to 0 timer 2 7) i t2ddc 200 a set pmcon1.t2_dis to 0 mdu 8) i mduddc 1260 a set pmcon1.mdu_dis to 0 cordic 9) i cordicddc 1880 a set pmcon1.cdc_dis to 0 ledtscu 10) i ledddc 850 a set pmcon1.lts_dis to 0 iic 11) i iicddc 580 a set pmcon1.iic_dis to 0
xc835/836 electrical parameters data sheet 37 v1.2, 2011-03 7) timer 2 active current is measured with: module enabled, timer running in 8 mhz 8) mdu active current is measured with: module enabled, division operation was performed. 9) cordic active mode is measured with: module enabl ed, circular mode was selected for the calculation. 10) ledtscu active curent is measured with: module enabled, counter running in 8 mhz. 11) iic active current is measured with: module enabled , performing a master transmit with the master clock running at 400 khz.
xc835/836 electrical parameters data sheet 38 v1.2, 2011-03 3.3 ac parameters the electrical characteristic s of the ac parameters are detailed in this section. 3.3.1 testing waveforms the testing waveforms for ri se/fall time, output delay and output high impedance are shown in figure 11 , figure 12 and figure 13 . figure 11 rise/fall time parameters figure 12 testing waveform, output delay figure 13 testing waveform , output high impedance 10% 90% 10% 90% v ss v ddp t r t f v dde / 2 test points v dde / 2 v ss v ddp v load + 0.1 v v oh - 0.1 v timing reference points v load - 0.1 v v ol - 0.1 v
xc835/836 electrical parameters data sheet 39 v1.2, 2011-03 3.3.2 output rise/fall times table 18 provides the characterist ics of the output rise/fall times in the xc835/836. figure 14 rise/fall times parameters table 18 output rise/fall times para meters (operating conditions apply) parameter symbol limit valu es unit test conditions min. max. rise/fall times on high current pad type a 1)2) 1) rise/fall time parameters are taken with 10% - 90% of supply. 2) not all parameters are 100% tested, but are verified by design/characterisation and test correlation. t hcpr , t hcpf ? 15 ns 20 pf @ fast edge (5 v) 3) . 3) additional rise/fall time valid for c l =20pf-c l = 100 pf @ 0.125 ns/pf at 5 v supply voltage. ? 150 ns 20 pf @ slow edge (5 v) 3) . ? 25 ns 20 pf @ fast edge (3.3 v) 4) . 4) additional rise/fall time valid for c l =20pf-c l = 100 pf.@ 0.225 ns/pf at 3.3 v supply voltage. ? 300 ns 20 pf @ slow edge (3.3 v) 4) . rise/fall times on high current pad type b 1)2) t r , t f ?10ns20 pf 3)4) (5 v & 3.3 v). rise/fall times on standard pad 1)2) t r , t f ?10ns20 pf 3)4) (5 v & 3.3 v). t r 10% 90% 10% 90% t f v ss v ddc
xc835/836 electrical parameters data sheet 40 v1.2, 2011-03 3.3.3 oscillator timing and wake-up timing table 19 provides the characteristics of the po wer-on reset, pll a nd wake-up timings in the xc835/836. table 19 power-on reset wake-up timing 1) (operating conditions apply) 1) not subject to production test, verified by design/characterisation. parameter symbol limit va lues unit test conditions min. typ. max. 48 mhz oscillator start-up time t 48moscst cc ? ? 13 s 75 khz oscillator start- up time t 75koscst cc ? ? 800 s 32 khz external oscillator start-up time 2) 2) the external circuitry has to be optimized by t he user and checked for negative resistance as recommended and specified by the crystal supplier. t 32koscst cc ? ? 1 s flash initialization time t fint cc ? 160 ? s
xc835/836 electrical parameters data sheet 41 v1.2, 2011-03 3.3.4 on-chip oscillator characteristics table 20 provides the characteristics of th e 48 mhz oscillator in the xc835/836. table 20 48 mhz oscillator characteri stics (operating conditions apply) parameter symbol limit va lues unit test conditions min. typ. max. nominal frequency f nom cc -0.5 % 48 +0.5% mhz under nominal conditions 1) after trimming 1) nominal condition: v ddc =2.5v, t a =+25 c. long term frequency deviation ? f lt cc -2.0 ? 3.0 % with respect to f nom , over lifetime and temperature (0 c to 85 c) -4.5 ? 4.5 % with respect to f nom , over lifetime and temperature (-40 c to 125 c) short term frequency deviation (over v ddc ) ? f st cc -1 ? 1 % with respect to f nom , within one lin message (< 10 ms ? 100 ms)
xc835/836 electrical parameters data sheet 42 v1.2, 2011-03 table 21 provides the characteristics of th e 75 khz oscillator in the xc835/836. table 21 75 khz oscillator characteri stics (operating conditions apply) parameter symbol limit va lues unit test conditions min. typ. max. nominal frequency f nom cc -1% 75 +1% khz under nominal conditions 1) after trimming 1) nominal condition: v ddc =2.5v, t a =+25 c. long term frequency deviation ? f lt cc -4.5 ? 4.5 % with respect to f nom , over lifetime and temperature (-40 c to 125 c) short term frequency deviation ? f st cc -1.5 ? 1.5 % with respect to f nom , over v ddc
xc835/836 electrical parameters data sheet 43 v1.2, 2011-03 3.3.5 ssc timing 3.3.5.1 ssc master mode timing table 22 provides the ssc master m ode timing in the xc835/836. figure 15 ssc master mode timing table 22 ssc master mode timing 1) (operating conditions apply; cl = 50 pf) 1) not subject to production test, verified by design/characterisation. parameter symbol limit values unit min. max. sclk clock period t 0 cc 2 * t ssc 2) 2) t sscmin =t cpu =1/ f cpu . when f cpu = 24 mhz, t 0 = 83.3 ns. t cpu is the cpu clock period. ?ns mtsr delay from sclk t 1 cc 0 3 ns mrst set-up to sclk t 2 sr 32 ? ns mrst hold from sclk t 3 sr 0 ? ns ssc_tmg1 sclk 1) mtsr 1) t 1 t 1 mrst 1) t 3 data valid t 2 t 1 1) this timing is based on the following setup: con.ph = con.po = 0. t 0
xc835/836 electrical parameters data sheet 44 v1.2, 2011-03 3.3.5.2 ssc slave mode timing table 23 provides the ssc slave mo de timing in the xc835/836. figure 16 ssc slave mode timing table 23 ssc slave mode timing 1) (operating conditio ns apply; cl = 50 pf) 1) not subject to production test, verified by design/characterisation. parameter symbol limit values unit min. max. sclk clock period t 0 sr 4 * t ssc 2) 2) t sscmin =t cpu =1/ f cpu . when f cpu = 24 mhz, t 0 = 166.7 ns. t cpu is the cpu clock period. ?ns mrst delay from sclk t 1 cc 0 29 ns mtsr set-up to sclk t 2 sr 32 ? ns mtsr hold from sclk t 3 sr 0 ? ns t 2 t 3 t 1 sclk 1) mtsr 1) mrst 1) t 0 data valid 1) this timing is based on the following setup : con.ph = con.po = 0.
xc835/836 electrical parameters data sheet 45 v1.2, 2011-03 3.3.6 spd timing the spd interface will work with standard spd tools havi ng a sample/output clock fre- quency deviation of +/- 5% or less. for further detail s please refer to application note ap24004 in section spd timing requirements. note: these parameters are no subject to pr oduct test but verifi ed by design and/or characterization. note: operating conditions apply.
xc835/836 package and quality declaration data sheet 46 v1.2, 2011-03 4 package and quality declaration chapter 4 provides the informatio n of the xc835/836 packa ge and reliability section. 4.1 package parameters table 24 provides the thermal characteristic s of the packages used in xc835 and xc836 respectively. table 24 thermal characte ristics of the packages parameter symbol limit va lues unit package types min. max. thermal resistan ce junction case 1) 1) the thermal resistances between the case and the ambient ( r tca ) , the lead and the ambient ( r tla ) are to be combined with the thermal resistances between the junction and the case ( r tjc ), the junction and the lead ( r tjl ) given above, in order to calculate the total t hermal resistance between the junction and the ambient ( r tja ). the thermal resistances between the case and the ambient ( r tca ), the lead and the ambient ( r tla ) depend on the external system (pcb, case) characte ristics, and are under user responsibility. the junction temperature can be calculated using the following equation: t j = t a + r tja p d , where the r tja is the total thermal resistance between the junction and t he ambient. this total junction ambient resistance r tja can be obtained from the upper four partial thermal resistances, by a) simply adding only the two thermal resistances (junction lead and lead ambient), or b) by taking all four resistances into account, depending on the precision needed. r tjc cc - 30.8 k/w pg-dso-24-1 - 27.0 k/w pg-tssop-28-1 - 20.2 k/w pg-tssop-28-12 thermal resistan ce junction lead 1) r tjl cc - 30.5 k/w pg-dso-24-1 - 195.3 k/w pg-tssop-28-1 - 41 k/w pg-tssop-28-12
xc835/836 package and quality declaration data sheet 47 v1.2, 2011-03 4.2 package outline figure 17 and figure 18 shows the package outlines of the xc835 (dso-24-1) and xc836 (tssop-28-1 and tssop-28 -12) devices respectively. figure 17 pg-dso-24-1 package outline
xc835/836 package and quality declaration data sheet 48 v1.2, 2011-03 figure 18 pg-tssop-28-1 package outline
xc835/836 package and quality declaration data sheet 49 v1.2, 2011-03 figure 19 pg-tssop-28-12 package outline
xc835/836 package and quality declaration data sheet 50 v1.2, 2011-03 4.3 quality declaration table 25 shows the characteristics of the quality parameters in the xc835/836. table 25 quality parameters parameter symbol limit values unit notes min. max. operation lifetime when the device is used at the three stated t j 1) 1) this lifetime refers only to the time when device is powered-on. t op1 - 1500 hours t j =150 c - 15000 hours t j =110 c - 1500 hours t j =-40 c operation lifetime when the device is used at the stated t j 1) t op2 - 131400 hours t j =27 c esd susceptibility according to human body model (hbm) v hbm - 2000 v conforming to eia/jesd22- a114-b 2) 2) not all parameters are 100% tested, but are verified by design/characterisation and test correlation. esd susceptibility according to charged device model (cdm) pins v cdm - 500 v conforming to jesd22-c101-c 2)
www.infineon.com published by infineon technologies ag

▲Up To Search▲

Price & Availability of SAF-XC836MT-2FRA

	To Download SAF-XC836MT-2FRA Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .